Wafer having pad structure

A PCM pad structure for carrying out integrated circuit testing and failure analysis, comprising:

• at least two metal pads connected there-between by a plurality of conductive vias;
• a plurality of contact bars in contact with a bottom-most metal pad, the contact bars extending substantially vertically from the bottom-most metal pad into the substrate;
• and
• an isolation structure substantially surrounding the plurality of contact bars to isolate the PCM pad structure.

A wafer comprising:

• at least two metal pads connected there-between by a plurality of vias;
• a plurality of contact bars in contact with a bottom-most metal pad of the at least two metal pads, wherein each contact bar of the plurality of contact bars extends vertically from the bottom-most metal pad into a substrate;
• and
• an isolation structure embedded in the substrate, wherein a bottom surface of at least one contact bar of the plurality of contact bars is coplanar with a top surface of the isolation.