Tunnel field-effect transistor and method for fabrictaing the same

A tunnel field-effect transistor component comprising:

• a substrate having a first-type well, a second-type well, and a shallow trench isolation feature separating the first-type well and the second-type well;
• a first-type tunnel field-effect transistor disposed on the second-type well, the first-type tunnel field-effect transistor comprising:
• a first-type drain layer;
• a second-type source layer;
• a first-type channel layer disposed between the first-type drain layer and the second-type source layer, wherein at least one of the first-type drain layer, the first-type channel layer, and the second-type source layer has a substantially constant doping concentration;
• a first metal gate layer disposed around the first-type channel layer;
• and
• a first high-k dielectric layer disposed between the first metal gate layer and the first-type channel layer;
• and
• a second-type tunnel field-effect transistor disposed on the first-type well, the second-type tunnel field-effect transistor comprising:
• a second-type drain layer;
• a first-type source layer;
• a second-type channel layer disposed between the second-type drain layer and the first-type source layer, wherein at least one of the second-type drain layer, the second-type channel layer, and the first-type source layer has a substantially constant doping concentration;
• a second metal gate layer disposed around the second-type channel layer;
• and
• a second high-k dielectric layer disposed between the second metal gate layer and the second-type channel layer.

A method for fabricating a tunnel field-effect transistor, comprising:

• forming a semiconductor wire structure on a substrate, wherein the semiconductor wire structure comprises a bottom source or drain layer formed on the substrate, a channel layer formed on the bottom source or drain layer, and a top source or drain layer formed on the channel layer, wherein at least one of the bottom source or drain layer, the channel layer, and top source or drain layer has a substantially constant doping concentration;
• forming a high-k dielectric layer around the channel layer;
• and
• forming a metal gate layer around the high-k dielectric layer.