Preventing buried oxide gouging during planar and finfet processing on soi
AssigneeInternational Business Machines Corporation
InventorsKern Rim, Junli Wang
Life of this patent
Estimating the term…
Abstract
A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations.
Claims20
A method for preventing damage to the insulator layer of a semiconductor device during fabrication of fin field effect transistor (FinFET) devices, the method comprising:
- obtaining a material stack comprising an active semiconductor layer, an insulator layer, and an etch stop layer existing between the active semiconductor layer and the insulator layer;
- forming a fin-array from the active semiconductor layer by applying fin-array formation processes to the material stack, with the etch stop layer resistant to those fin-array formation processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during fin-array formation;
- patterning the fin-array by applying fin-array patterning processes after the fin-array has been formed from the active semiconductor layer, with the etch stop layer resistant to those fin-array patterning processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during fin-array patterning;
- and
- fabricating a FinFET device by applying FinFET fabrication processes after the fin-array has been patterned by the fin-array patterning processes, with the etch stop layer resistant to those FinFET fabrication processes that the etch stop layer is exposed to, such that the etch stop layer and the insulator layer are not damaged during FinFET fabrication.
A structure for manufacturing a semiconductor device without damaging the insulator layer during creation of fin field effect transistor (FinFET) devices, comprising:
- an insulator layer;
- an active semiconductor layer;
- and
- an etch stop layer comprising material resistant to those processes the etch stop layer is exposed to during creation of a FinFET having fins formed from the active semiconductor layer, such that the etch stop layer and the insulator layer are not damaged during creation of the FinFET;
- wherein, the etch stop layer is between the insulator layer and the active semiconductor layer.
A structure for manufacturing semiconductor devices without damaging the insulator layer during creation of fin field effect transistor (FinFET) devices, comprising:
- an insulator layer;
- a patterned fin-array comprising active semiconductor material;
- and
- an etch stop layer comprising material resistant to (i) those processes the etch stop layer is exposed to during formation and patterning of the patterned fin-array, and (ii) those processes the etch stop layer is exposed to during fabrication of a FinFET device having a fin of the patterned fin-array, such that the etch stop layer and the insulator layer are not damaged during the formation, patterning, and fabrication;
- wherein, the etch stop layer is between the insulator layer and the patterned fin-array.
Dependencies are inferred from the claim text.