Method of Semiconductor Integrated Circuit Fabrication

A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

• forming a dielectric layer over a substrate;
• forming an interlayer over the dielectric layer;
• forming a first photoresist (PR) layer over the dielectric layer;
• forming a second PR layer over the first PR layer;
• forming a first opening in the second PR layer and the second opening in the first PR layer by performing a single exposure process;
• forming spacers along opposing sidewalls of the first and second openings;
• performing a first etching process to the interlayer to form a first trench extending through the first etched interlayer while using the spacers along the second opening as an etch mask;
• performing the first etching process to the first PR layer to form a second trench while using the spacers along the first opening as an etch mask;
• performing a second etching process to the first etched interlayer to form a third trench extending through the second etched interlayer and into the dielectric layer;
• performing the second etching process to the first etched PR layer to form a fourth trench extending through the first etched the first PR layer and into the interlayer;
• performing a third etching process to the second etched dielectric layer and the second etched interlayer to form a dielectric trench in the dielectric layer that includes an upper portion having a second width and a lower portion having a first width that is different than the second width.

A method for fabricating a semiconductor integrated circuit (IC), the method comprising:

• forming a dielectric layer over a substrate;
• forming a first photoresist (PR) layer with a first opening over the dielectric layer;
• forming a second PR layer with a second opening over the first PR Layer, wherein the first and second PR layers received a single exposure process;
• forming spacers along opposing sidewalls of the first and second openings;
• forming a lower portion of a dielectric trench in the dielectric layer while using the spacer along the first opening as an etch mask;
• and
• forming an upper portion of the dielectric trench in the dielectric layer while using the spacer along the second opening as an etch mask.