Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKatsuyuki Fujita
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Abstract
According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
Claims1
A semiconductor memory device comprising:
- a memory cell array comprising memory cells;
- a redundancy area comprising redundancy cells which are used for failure cells in the memory cell array;
- first word lines connected to the memory cell array;
- second word lines connected to the redundancy area;
- a first row decoder configured to perform selecting from the first word lines based on a row address;
- a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address;
- and
- a second row decoder configured to perform selecting from the second word lines based on a determination result by the judgment circuit,
- wherein the row address includes a first row address and a second row address input in order in a time-sharing method, and
- the first row address includes all of the redundancy address.
Dependencies are inferred from the claim text.