Memory tester design for soft error rate (ser) failure analysis

A computer system for determining a multi-bit upset (MBU) during soft error rate (SER) testing of a memory device under test, the computer system comprising:

• one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage mediums, and program instructions stored on at least one of the one or more storage mediums for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising:
• receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device, the error indication associated with error information corresponding to the comparison between the generated test data pattern and the stored version of the generated test data pattern;
• determining, based on the received error indication, a count value associated with one of a predetermined number of passes that a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device;
• and
• determining the MBU based on the address location, the error information, and the determined count value.

A computer program product for determining a multi-bit upset (MBU) during soft error rate (SER) testing of a memory device under test, comprising:

• one or more tangible computer-readable storage mediums and program instructions stored on at least one of the one or more tangible storage mediums, the program instructions executable by a processor, the program instructions comprising:
• receiving an error indication based on a comparison between a generated test data pattern written to an address location on the memory device and a stored version of the generated test data pattern read from the address location on the memory device, the error indication associated with error information corresponding to the comparison between the generated test data pattern and the stored version of the generated test data pattern;
• determining, based on the received error indication, a count value associated with one of a predetermined number of passes that a plurality of generated test data patterns traverse between a first and a second memory address location on the memory device;
• and
• determining the MBU based on the address location, the error information, and the determined count value.