US 2015/0318048 A1Published application

Non-Volatile Semiconductor Storage Device

AssigneeFloadia Corporation

InventorsHideo Kasai, Yutaka Shinagawa, Yasuhiro Taniguchi

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Abstract

To propose a non-volatile semiconductor memory device capable of suppressing occurrence of disturbance more greatly than in a conventional technique while achieving miniaturization. A plurality of word lines are formed in a matrix in the non-volatile semiconductor memory device, power supply units are respectively provided for word line columns (memory wells), a different unit voltage is applied for each of power supply units depending on whether or not a selected memory cell exists in the word line column, a switching mechanism in each of the power supply units is switched by the word line depending on a value of a voltage on a control line, a charge storage gate voltage or a charge storage inhibition gate voltage is individually applied for each of the word lines so that the charge storage inhibition gate voltage value and a bit line voltage value can be freely set for each of the word line columns to values at which occurrence of disturbance can be suppressed. A plurality of power supply units are connected to the control line in a common row direction, and a row-direction address decoder, which is independent for each of the word line columns is not required so that the non-volatile semiconductor memory device can be miniaturized.

Claims12

Dependent claims

A non-volatile semiconductor memory device comprising a plurality of word lines formed in a matrix to which either one of a charge storage gate voltage and a charge storage inhibition gate voltage is applied, a plurality of memory cells connected to the respective word lines, and a bit line that applies a selective voltage to the plurality of memory cells, a charge being stored in selected one of the plurality of memory cells due to a voltage difference between the charge storage gate voltage applied to the word line and the voltage applied to the bit line,

further comprising power supply units respectively provided for word line columns and common wirings respectively provided for word line rows, each of the common wirings applying a predetermined common voltage to the power supply units on a word-line-row basis,
each of the power supply units including
switching mechanisms that are respectively provided for the word lines and respectively connect the word lines to the common wirings, and
a unit wiring that uniformly applies different unit voltages to each of the switching mechanisms in the power supply unit depending on whether or not the selected memory cell exists in the word line column, wherein
the switching mechanisms in each of the power supply units are turned on or off based on a voltage difference between the unit voltages applied to each of the power supply units and the common voltage, to individually apply the charge storage gate voltage or the charge storage inhibition gate voltage to each of the word lines via the power supply unit.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/410,380Filed 21 Jun 2013
Priority: JP 2012-14695429 Jun 2012
Published: 5 Nov 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 16/0466
Using variable threshold transistors, e.g. FAMOS: comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits