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AssigneeInternational Business Machines Corporation
InventorsSheikh Sabiq Chishti, Toshiaki Kirihata, Krishnan S. Rengarajan, Deepal Wehella-Gamage
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A method generating a default state in an embedded Multi-Time-Programmable-Read-Only-Memory for a high-performance logic technology consisting of a plurality of memory cells featuring a charge trap, each having a first and a second NMOS transistor. The first and second NMOS transistors use a different mask having different threshold voltages. The second NMOS threshold voltage is adjusted to a middle point of the threshold voltage of the first NMOS with or without trapping the charge. When the charge is not trapped by the first NMOS, the NMOS threshold is lowered to the second NMOS, thereby generating a default state. When the charge is trapped to the first NMOS, the NMOS threshold is higher than the second NMOS, generating a second state. Moreover, a reference voltage generation can use two arrays, each consisting of memory cells and reference memory cells such that a default state can be generated for a single transistor per memory cell.
An Embedded Multi-Time-Read-Only-Memory (eMTPROM) comprising:
A method of generating a default state comprising forming an array consisting of a plurality of cells, each of said cells having first NMOS having a first threshold voltage VT1 without trapping said charge and a second NMOS having a second threshold voltage VT2, wherein said VT2 is different from VT1.
A method of generating a default state comprising a first and second sub-arrays, each of said sub-arrays consisting of a plurality of memory cells coupled to wordlines, and at least one reference wordline coupled to a plurality of said reference memory cells, wherein said memory cell and said reference memory cells have different threshold voltages.
A method of generating a default state comprising first and second sub-arrays, each consisting of plurality of memory cells coupled to wordlines, and at least one reference wordline coupled to a plurality of reference memory cells, wherein said memory cell and said reference memory cells have same threshold voltages, wherein said state of trapped or untrapped state of said memory cell are detected by enabling an activation of said wordline coupled to the memory cells in a first array by a first wordline voltage, and enabling the activation of said reference wordline coupled to said reference memory cells in a second array by a second wordline voltage, developing said first bitline voltage on a corresponding bitline in said first array, and said second bitline voltage on the corresponding bitline in the second array, wherein said corresponding bitlines in said first and said second array are coupled by a differential sense amplifier, outputting said first state for said un-trapped memory cell, and said second state for said trapped said memory cell or vise versa.
The method of claim in 17, wherein said second voltage is lower than said first voltage by one half of a level of differential threshold voltage of said memory cells defining a first state for said un-trapped memory cell, and a second state for said trapped memory cell.
Dependencies are inferred from the claim text.