Apparatuses and methods for controlling a clock signal provided to a clock tree

A method, comprising:

• receiving a plurality of write commands at a memory device;
• enabling on-die termination (ODT) circuitry responsive to receipt of a first write command of the plurality of write commands;
• detecting a next write command of the plurality of write commands within a consecutive write command period responsive to the first write command being output from a write command register;
• and
• disabling a clock signal provided to a clock tree responsive to detection of the next write command signal within a consecutive write command period.

An apparatus comprising:

• an on-die termination (ODT) enable latch configured to latch an ODT enable signal each time a clock signal is asserted;
• a write command detection circuit configured to output a detection signal when consecutive assertion of a plurality of write commands are detected;
• and
• a control circuit configured to stop asserting the clock signal responsive, at least in part, to the detection signal.