Memory device with reduced operating current
AssigneeSamsung Electronics Co., Ltd.
InventorHYUN-KOOK PARK
Life of this patent
Estimating the term…
Abstract
A memory device may including a first local bit line electrically connected with a first memory cell, a first global bit line electrically connected with the first local bit line, a second local bit line electrically connected with a second memory cell, and a second global bit line electrically connected with the second local bit line. The first global bit line is primarily charged with electric charge. The first global bit line and the second global bit line share the primarily charged electric charge. The second global bit line is secondarily charged with the electric charge.
Claims20
A memory device comprising:
- a first local bit line electrically connected with a first memory cell;
- a first global bit line electrically connected with the first local bit line;
- a second local bit line electrically connected with a second memory cell;
- and
- a second global bit line electrically connected with the second local bit line,
- wherein the first global bit line is configured to be primarily charged with electric charge,
- the first global bit line and the second global bit line are configured to share the primarily charged electric charge, and
- the second global bit line is secondarily charged with the electric charge.
A memory device comprising:
- a normal local bit line electrically connected with a normal memory cell;
- a normal global bit line electrically connected with the normal local bit line;
- a dummy local bit line electrically connected with a dummy memory cell;
- a dummy global bit line electrically connected with the dummy local bit line and precharged with a target voltage;
- a read/write circuit configured to read data by providing read current to the normal memory cell and/or to write data by providing write current to the normal memory cell;
- and
- a precharge circuit configured to precharge the dummy global bit line,
- wherein the precharged dummy global bit line and the normal global bit line are electrically connected with each other, before reading or writing the normal memory cell.
A memory card comprising:
- a non-volatile memory device;
- and
- a controller configured to control the non-volatile memory device,
- wherein the non-volatile memory device includes:
- a first local bit line electrically connected with a first memory cell;
- a first global bit line electrically connected with the first local bit line;
- a second local bit line electrically connected with a second memory cell;
- a second global bit line electrically connected with the second local bit line;
- and
- a read/write circuit configured to charge the first memory cell and/or the second memory cell, and
- wherein when first data is written in the second memory cell, the first global bit line and the second global bit line share electric charge before providing first write current to the second memory cell, and
- when second data other than the first data is written in the second memory cell, the first global bit line and the second global bit line do not share electric charge before providing second write current to the second memory cell.
Dependencies are inferred from the claim text.