Shift Register and Display Device Using the Same

A shift register comprising a plurality of stages, the shift register configured to drive gate lines of a display device,

• wherein each of the plurality of stages includes:
• an output unit configured to output any one input clock of a plurality of clocks or a gate off voltage in response to logic states of a first control node and a second control node;
• a noise cleaner configured to connect a previous output for a current stage and the first control node in response to a previous clock used in a previous stage as a previous output for the current stage at any one of previous stages;
• and
• a controller configured to control the second control node to have a logic state opposite to the logic state of the first control node in some periods, and
• wherein the noise cleaner includes:
• first and second transistors connected between the first control node and the previous output for the current stage in series to connect the first control node and the previous output for the current stage in response to a logic state of the previous clock for the current stage, and
• a third transistor configured to supply an offset voltage to a connection node between the first and second transistors in response to the logic state of the first control node.