US 2015/0317427 A1 · INTEGRATED CIRCUIT DESIGN SYSTEM AND METHOD OF USING THE SAME

Abstract

A system for designing an integrated circuit includes at least one processor and at least one memory including computer program code for one or more programs. The at least one memory and the computer program code are configured to, with the at least one processor, cause the system to receive a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from a set of system design rule constraints. The system is also caused to revise a schematic of the integrated circuit including the proposed device array layout. The system is further caused to determine whether the revised schematic violates one or more system design rule constraints.

Claims20

Dependent claims

A system for designing an integrated circuit, the system comprising:

at least one processor;
and
at least one memory including computer program code for one or more programs, the at least one memory and the computer program code configured to, with the at least one processor, cause the system to:
receive a proposed device array layout from a device array design module, the device array design module being configured to generate the proposed device array layout free from a set of system design rule constraints;
revise a schematic of the integrated circuit including the proposed device array layout;
and
determine whether the revised schematic violates one or more system design rule constraints.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/799,762Filed 15 Jul 2015

Priority

29 Nov 2013

Published

5 Nov 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G06F 30/39
Circuit design: circuit design at the physical level
G06F 30/392
Circuit design at the physical level: floor-planning or layout, e.g. partitioning or placement
G06F 2111/04
Details relating to CAD techniques: constraint-based CAD

Family

Application61/910,172Us provisional application · filed 29 Nov 2013

Application14/193,527Continuation · filed 28 Feb 2014

Application14/799,762Continuation

US 2015/0154333 A1Published application

US 9,092,589 B2Related patent

US 9,418,200 B2Related patent

US 2015/0317427 A1This patent

From the US filing history. Foreign family members aren’t listed.

Integrated circuit design system and method of using the same

Life of this patent

Integrated circuit design system and method of using the same

Life of this patent

Abstract

Claims20