Method and apparatus for dummy cell placement management

A system for manipulating a circuit design comprising:

• a data repository for storing the circuit design;
• a computer processor;
• a dummy cell manager executing on the computer processor for causing the computer processor to:
• select, based on a plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design,
• generate, in the dummy cell insertion region, a plurality of dummy cells;
• select a first dummy cell from the plurality of dummy cells,
• determine, based on a location of the first dummy cell, an illegal overlap with the first dummy cell,
• remove, from the plurality of dummy cells, the first dummy cell, and
• insert, on the circuit design and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design;
• and
• a graphical user interface executing on the computer processor for causing the computer processor to:
• receive the plurality of dummy cell modification parameters, and
• present the modified circuit design.

A non-transitory computer readable medium storing instructions for manipulating a circuit design, the instructions comprising functionality to:

• receive a plurality of dummy cell modification parameters;
• select, based on the plurality of dummy cell modification parameters, a dummy cell insertion region on the circuit design;
• generate, in the dummy cell insertion region, a plurality of dummy cells;
• select a first dummy cell from the plurality of dummy cells;
• determine, based on a location of the first dummy cell, an illegal overlap with the first dummy cell;
• remove, from the plurality of dummy cells, the first dummy cell;
• insert, on the circuit design and after removing the first dummy cell, the plurality of dummy cells to obtain a modified circuit design;
• and
• present the modified circuit design.