System and method for optimization of an imaged pattern of a semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Ming Chang, Ming-Yo Chung, Tzu-Chun Lo, Ying-Hao Su
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Abstract
In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.
Claims20
A method, comprising:
- receiving a layout of a device having a first feature and a second feature on a first layer of the layout, wherein the first feature and the second feature are each symmetrical;
- determining a first criticality of an edge of the first feature, wherein the criticality is determined based on a third feature defined by a second layer of the layout;
- determining a first optimized lithography parameter associated with the edge of the first feature based on the determined first criticality;
- and
- using a photomask having the first feature and the second feature defined to image the first and second features onto a semiconductor substrate, wherein the using the photomask to image includes using the determined first optimized lithography parameter, and wherein the imaged first and second features are each asymmetrical.
A method, comprising:
- providing a layout of a device having a symmetrical feature;
- determining at least one optimization parameter based on an assigned image criteria for an identified first edge of the symmetrical feature;
- and
- fabricating an integrated circuit (IC), wherein the fabricating the IC includes imaging the first edge of the symmetrical feature onto a semiconductor substrate using the determined at least one optimization parameter;
- wherein the symmetrical feature is defined by a layout file, wherein the imaging provides an imaged feature on the semiconductor substrate, and wherein the imaged feature is asymmetrical.
A method, comprising:
- providing a layout of a device having a plurality of features;
- providing a baseline image criteria for a first portion of at least one feature of the plurality of features;
- assigning an image criteria for the first portion of the at least one feature of the plurality of features, wherein the assigned image criteria for the first portion is based on a first amount of deviation from the baseline image criteria;
- determining a first lithography optimization parameter based on the assigned image criteria for the first portion;
- and
- imaging the first portion of the at least one feature onto a semiconductor substrate using the determined first lithography optimization parameter;
- wherein the at least one feature is symmetrical as defined by a layout file, wherein the imaging provides an imaged first feature on the semiconductor substrate, and wherein the imaged first feature is asymmetrical.
Dependencies are inferred from the claim text.