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US 2015/0317277 A1Published application
Computer architecture having selectable, parallel and serial communication channels between processors and memory
AssigneeWisconsin Alumni Research Foundation
InventorsHao Wang, Nam Sung Kim
Life of this patent
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Abstract
A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application.
Claims20
An electronic computer comprising:
- a processor system having:
- (a) a first latency-sensitive processor executing a general instruction set for general purpose computation;
- (b) a second latency-insensitive processor executing a specialized instruction set for specialized computation, wherein the latency-insensitive processor is less sensitive to latency in access to electronic memory than the latency-sensitive processor;
- an electronic memory communicating with the processor system and storing data words for reading and writing by the processor system;
- a parallel bus communicating between the processor system and the memory providing transmission of different bits of given data words in parallel on separate conductors of a parallel lane;
- a serial bus communicating between the processor system and the memory providing transmission of different bits of given data words serially on at least one conductor of a serial lane;
- and
- a memory access manager preferentially routing memory access by the latency-sensitive processor through the parallel bus and memory access by the latency-insensitive processor through the serial bus.
5 more elements
An electronic memory device comprising:
- a package housing providing a set of conductive terminal points allowing electrical communication from circuitry within the package housing to circuitry outside of the package housing;
- and
- an integrated circuit held within the package housing and including:
- at least one storage element providing memory cells for storage and access of data words, the memory cells arranged in addressable logical rows and columns according to an address word;
- and
- a serial interface communicating with the storage element providing serial communication of data words where different bits of given data words and address words are communicated between the storage element and circuitry outside the package housing through at least one terminal point.
3 more elements
Dependencies are inferred from the claim text.