Semiconductor device and memory system

A semiconductor device, comprising:

• a semiconductor memory capable of holding data;
• and
• a controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus,
• wherein the controller circuit selects one of a first symbol and a second symbol in a random order, performs 8b/10b coding for the selected symbol, and transmits the 8b/10b coded symbol to the host apparatus,
• wherein the first and second symbols indicate an idle state,
• wherein the 8b/10b coded symbol is repeatedly transmitted to the host apparatus,
• wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and
• wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

A semiconductor device, comprising:

• a semiconductor memory capable of holding data;
• and
• a controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus,
• wherein the controller circuit selects one of a first symbol and a second symbol in a random order, selects a third symbol which indicates a delimiter, performs 8b/10b coding for the selected symbol, and transmits the 8b/10b coded symbol to the host apparatus,
• wherein a symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,
• wherein the symbol set is used to set up synchronization with the host apparatus,
• wherein each of the first and second symbols includes a pair of symbols including a symbol as a plus running disparity and another symbol as a minus running disparity, and
• wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

A semiconductor device, comprising:

• a semiconductor memory capable of holding data;
• and
• a controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus,
• wherein the controller circuit selects one of a first symbol and a second symbol in a random order, performs 8b/10b coding for the selected symbol, and transmits the 8b/10b coded symbol to the host apparatus,
• wherein the first and second symbols indicate an idle state,
• wherein the 8b/10b coded symbol is repeatedly transmitted to the host apparatus,
• wherein one of the first and second symbols is a symbol in which running disparity becomes ±0, and
• wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.

A semiconductor device, comprising:

• a semiconductor memory capable of holding data;
• and
• a controller circuit capable of accessing the semiconductor memory based on a command from a host apparatus,
• wherein the controller circuit selects one of a first symbol and a second symbol in a random order, selects a third symbol which indicates a delimiter, performs 8b/10b coding for the selected symbols, and transmits 8b/10b coded symbols to the host apparatus,
• wherein a symbol set including the 8b/10b coded one of the first and second symbols and the 8b/10b coded third symbol is repeatedly transmitted to the host apparatus,
• wherein the symbol set is used to set up synchronization with the host apparatus,
• wherein one of the first and second symbols is a symbol in which running disparity becomes ±0, and
• wherein a symbol selected by the controller circuit has a running disparity different from that of a symbol which is most recently selected by the controller circuit.