Switching a computer system from a high performance mode to a low power mode

A computer system, comprising:

• a common memory;
• a first processor connected to the common memory, the first processor including:
• one or more central processing unit (CPU) cores;
• a memory controller hub in communication with each of the CPU cores;
• one or more memory controllers in communication with the memory controller hub and the common memory;
• a bidirectional communication protocol controller in communication with the memory controller hub;
• and
• a memory bus connected to the common memory;
• a second processor in communication with the first processor, the second processor including:
• one or more CPU cores;
• a memory controller hub in communication with each of the CPU cores;
• one or more memory controllers in communication with the memory controller hub and the common memory;
• a bidirectional communication protocol controller in communication with the memory controller hub;
• and
• a memory bus connected to the common memory;
• and
• a polymorphous link between the first processor and the second processor, whereby the first processor may access the common memory through the polymorphous link.