US 2015/0317266 A1Published application

CONFIGURABLE PERIPHERAL COMPONENENT INTERCONNECT EXPRESS (PCIe) CONTROLLER

AssigneeFreescale Semiconductor, Inc.

InventorsDAVID B. KRAMER, Thang Q. Nguyen

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Abstract

In an system on a chip, multiple PCIe controllers may be present in which each PCIe controller may be configured to route input data to either itself or to another PCIe controller based on a priority level of the input data. Similarly, each PCIe controller may be configured to route output data by way of its own PCIe link or that of another PCIe controller based on a scheduling order which may be based on a priority level of the buffer in which the output data is stored. In this manner, multiple PCIe controllers which, in a first mode, are capable of operating independently from each other can be configured, in a second mode, to provide multiple channels for a single PCIe link, in which each channel may correspond to a different priority level.

Claims20

Dependent claims

A peripheral component interconnect express (PCIe) controller comprising:

an ingress buffer;
an egress buffer;
a first ingress transaction-level selection logic configured to select a first or a second data input signal as an ingress data signal, wherein:
the second data input signal originates from a second PCIe controller;
and
the first ingress transaction-level selection logic is enabled by a configuration signal;
a second ingress transaction-level selection logic communicatively coupled to the first ingress transaction-level selection logic, the second ingress transaction-level selection logic configured to:
receive the ingress data signal from the first ingress transaction-level selection logic;
and
communicate the ingress data signal to the ingress buffer or a second packet decoder based at least on an ingress transaction steering signal, wherein the ingress transaction steering signal is configured to indicate a priority level associated with the ingress data signal, the priority level having been decoded at a transaction level by a first packet decoder;
and
an egress transaction-level selection logic configured to select a first or a second data output signal to an egress data signal, wherein:
the second data output signal originates from the second PCIe controller;
and
the egress transaction-level selection logic is enabled by an egress transaction steering signal, the egress transaction steering signal configured to indicate a scheduling order associated with the PCIe controller and the second PCIe controller.

12 more elements

A peripheral component interconnect express (“PCIe”) controller comprising:

a data link layer configured to:
receive a first data input from a PCIe link;
receive a second data input from a second PCIe controller;
and
selectively decode a transaction-level packet from either the first or second data input in order to determine a priority level associated with the transaction-level packet;
and
generate an ingress transaction steering signal based at least on the priority level;
and
a transaction layer configured to:
receive the first or second data inputs from the data link layer;
receive the ingress transaction steering signal from the data link layer;
receive a first data output signal from a fabric communicatively coupled to the PCIe controller;
receive a second data output signal from the second PCIe controller;
selectively communicate the first or second data output signal to the data link layer based at least on a scheduling order associated with the PCIe controller and the second PCIe controller;
and
selectively communicate the first or second data inputs to the fabric or the second PCIe controller based at least on the priority level associated with the transaction-level packet, wherein the priority level associated with the PCIe controller is different from the priority level associated with the second PCIe controller.

13 more elements

An apparatus comprising:

a processor;
a fabric communicatively coupled to the processor;
and
a plurality of PCIe controllers communicatively coupled to the fabric, wherein each of
the plurality of PCIe controllers are communicatively coupled to one or more of its neighboring PCIe controllers, each of the plurality of PCIe controller comprising:
a data link layer configured to:
receive a first data input signal from a PCIe link;
receive a second data input signal from a second PCIe controller, the second PCIe controller being one of the plurality of PCIe controllers and one of the neighboring PCIe controllers;
and
selectively decode a transaction-level packet from either the first or second data input signal in order to determine a priority level associated with the transaction-level packet;
and
generate an ingress transaction steering signal based at least on the priority level;
and
a transaction layer configured to:
receive the first or second data input signal from the data link layer;
receive the ingress transaction steering signal from the data link layer;
receive a first data output signal from a fabric communicatively coupled to the PCIe controller;
receive a second data output signal from the second PCIe controller;
selectively communicate the first or second data output signal to the data link layer based at least on a scheduling order associated with the PCIe controller and the second PCIe controller;
and
selectively communicate the first or second data input signals to the fabric or the second PCIe controller based at least on the priority level associated with the transaction-level packet,
wherein the priority level associated with the PCIe controller is different from the priority level associated with the second PCIe controller.

19 more elements

Dependencies are inferred from the claim text.