US 2015/0317263 A1 · SYSTEMS AND METHODS FOR CONTROLLING A MEMORY PERFORMANCE POINT

Abstract

A system includes a processor, memory coupled to the processor by way of an interconnect, and monitoring hardware coupled to the interconnect. The memory operates at least at a first and second performance point where the first performance point has a higher performance than the second performance point. The monitoring hardware monitors transactions on the interconnect to a detect usage level of the interconnect and transmits an indication of the detected usage level to control logic. Based on the detected usage level being above a first threshold, the control logic causes the memory to operate at the first performance point. Based on the detected usage level being below a second threshold, the control logic causes the memory to operate at the second performance point. The second threshold is equal to or less than the first threshold.

Claims20

Dependent claims

A system, comprising:

a processor;
memory coupled to the processor by way of an interconnect, the memory configured to operate at least at a first and second performance point, the first performance point having a higher performance than the second performance point;
and
monitoring hardware coupled to the interconnect, the monitoring hardware configured to:
monitor transactions on the interconnect to a detect usage level of the interconnect;
and
transmit an indication of the detected usage level to control logic, the control logic configured to:
based on the detected usage level being above a first threshold, cause the memory to operate at the first performance point;
and
based on the detected usage level being below a second threshold, cause the memory to operate at the second performance point;
wherein the second threshold is equal to or less than the first threshold.

8 more elements

A method, comprising:

monitoring transactions on an interconnect and detecting usage level of the interconnect, wherein the interconnect couples a memory to a processor;
based on the detected usage level being above a first threshold, causing the memory to operate at a first performance point;
and
based on the detected usage level being below a second threshold, causing the memory to operate at a second performance point;
wherein the first performance point has a higher performance than the second performance point;
and
wherein the second threshold is equal to or less than the first threshold.

4 more elements

A system, comprising:

hardware logic including monitoring logic and control logic, the monitoring logic configured to:
monitor transactions on an interconnect between a processor and memory to detect a usage level of the interconnect;
and
transmit an indication of the detected usage level to the control logic, the control logic configured to:
based on the detected usage level being above a first threshold, cause the memory to operate at the first performance point;
and
based on the detected usage level being below a second threshold, cause the memory to operate at the second performance point;
wherein the second threshold is equal to or less than the first threshold.

5 more elements

Dependencies are inferred from the claim text.

Systems and methods for controlling a memory performance point

Life of this patent

Systems and methods for controlling a memory performance point

Life of this patent

Abstract

Claims20