Memory access monitor
AssigneeAdvanced Micro Devices, Inc.
InventorsJaewoong Chung, Shekhar Srikantaiah, Lisa Hsu
Life of this patent
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Abstract
For each access request received at a shared cache of the data processing device, a memory access pattern (MAP) monitor predicts which of the memory banks, and corresponding row buffers, would be accessed by the access request if the requesting thread were the only thread executing at the data processing device. By recording predicted accesses over time for a number of access requests, the MAP monitor develops a pattern of predicted memory accesses by executing threads. The pattern can be employed to assign resources at the shared cache, thereby managing memory more efficiently.
Claims31
At a data processing device comprising a plurality of processor cores, a shared cache, and a memory including a plurality of memory banks, a method comprising:
- replacing cache lines at the shared cache, such that a subset of the cache lines associated with threads having a higher spatial locality are assigned a higher replacement priority than a subset of the cache lines associated with threads having a higher temporal locality.
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A method, comprising:
- identifying a first spatial locality for a first thread at a processor, the first spatial locality indicating a size of a first range of memory addresses fetched to a cache of the processor for the first thread;
- identifying a second spatial locality for a second thread at a processor, the second spatial locality indicating a size of a second range of memory addresses fetched to a cache of the processor for the second thread;
- and
- prioritizing replacement of data at the cache based on the first spatial locality and the second spatial locality.
A data processing device, comprising:
- a plurality of processor cores;
- a shared cache coupled to each of the plurality of processor cores, the shared cache to receive a plurality of access requests from the plurality of processor cores;
- a memory comprising a plurality of memory banks;
- a storage location to store, based on the plurality of access requests, data representative of a predicted pattern of accesses to the plurality of memory banks;
- and
- a cache controller to replace cache lines at the shared cache, such that a subset of the cache lines associated with threads having a higher spatial locality are assigned a higher replacement priority than a subset of the cache lines associated with threads having a higher temporal locality.
Dependencies are inferred from the claim text.