Controller circuits, data interface blocks, and methods for transferring data
AssigneeNXP B.V.
InventorsNicolas Laine, Cyril Edeline
Life of this patent
Estimating the term…
Abstract
A processor circuit, with: a processor unit configured to execute a multiple load or multiple store instruction for loading or storing a plurality of data words; a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save the state of the multiple load or store instruction. Saving the state can comprise storing the number of data words already loaded or stored when the interrupt occurred. When the multiple load/store instruction is executed again after the interrupt, the DIB can skip the stored number of data words.
Claims15
Processor circuit, comprising:
- a processor unit configured to execute a multiple load or store instruction for loading or storing a plurality of data words;
- a data interface block, DIB, configured to communicate with the processor and configured to, in response to an occurrence of an interrupt during execution of the multiple load or store instruction, save a state of the multiple load or store instruction.
Method for loading or storing a plurality of data words, the method comprising:
- executing, in a processor unit, a multiple load or store instruction;
- writing at least one data word to a data interface block, DIB;
- detecting an occurrence of an interrupt of the processor unit;
- signaling to the DIB that the multiple load or store instruction is interrupted;
- storing, by the DIB, a state of the multiple load or store instruction.
Dependencies are inferred from the claim text.