Kick-started run-to-completion processor having no instruction counter

A pipelined processor adapted to be coupled to a memory system, comprising:

• an input data port;
• an initial fetch information port;
• an output data port;
• a fetch stage that issues memory requests to the memory system, wherein the fetch stage is prompted to issue a memory request in response to receiving fetch information from the initial fetch information port, and wherein the fetch stage is prompted to issue a memory request in response to receiving fetch information supplied from another stage of the pipelined processor;
• a fetch shift selector stage that receives a block of instructions from the memory system in response to each fetch request issued by the fetch stage, wherein the fetch shift selector stage stores a block of instructions and outputs one selected instruction from the block of instructions;
• a decode stage that controls the fetch shift selector stage so that the fetch shift selector stage outputs said one selected instruction, wherein the decode stage decodes the selected instruction as output from the fetch shift selector stage, and wherein the decode stage maintains an A register pointer, an B register pointer, and an input data pointer;
• a register file read stage that comprises a register file and an input data register, wherein the input data register is loaded with input data from the input data port, wherein the register file read stage uses the A register pointer, the B register pointer, and the input data pointer to read various parts of the register file and the input data register, and wherein register file read stage outputs contents of the register file onto the output data port;
• and
• an execute stage that receives said various parts from the register file read stage, wherein the execute stage includes an ALU (Arithmetic Logic Unit), wherein the execute stage can output fetch information to the fetch stage such that the fetch stage is prompted to output a memory request, wherein the pipelined processor comprises no instruction counter, and wherein the pipelined processor only performs an instruction fetch in response to receiving fetch information through the initial fetch information port or due to execution by the pipelined processor of a fetch instruction that is decoded by the decode stage.

A processor comprising:

• means for fetching blocks of information from a memory system external to the processor without the use of an instruction counter, wherein the means only fetches blocks of information from the memory system in response to either a receiving of fetch information onto the processor from an external source or to a receiving of fetch information from the execute stage, wherein the processor includes no instruction counter and the means fetches blocks of information without use of any instruction counter;
• a decode stage coupled to the means, wherein the decode stage can decode a fetch instruction;
• a register file read stage coupled to the decode stage;
• and
• an execute stage coupled to the register file read stage, wherein the execute stage executes the fetch instruction by outputting fetch information to the fetch request stage thereby prompting the means to fetch a block of information.