Approximating Functions

A computer-implemented method of deriving a hardware representation of a binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments, the method comprising:

• fitting, by a processor, a plurality of linear segments to the function over the predefined range, each segment extending between a pair of break points and having a fixed gradient selected from a predetermined set of fixed gradients,
• determining a base value for each of the segments;
• and
• deriving, by a processor, a hardware representation for a binary logic circuit which comprises:
• for each of the plurality of linear segments:
• a binary multiplier adapted to perform multiplication by the selected fixed gradient of the segment using h−1 binary adders, where h is the minimum Hamming weight of:
• a binary representation of the fixed gradient;
• a trinary representation of the fixed gradient;
• and
• a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary number;
• wherein the h−1 binary adders are logically configured to perform multiplication using the representation of the fixed gradient having the minimum Hamming weight h;
• and
• a binary adder adapted to add the determined base value to the input or output of the binary multiplier;
• and
• selection logic adapted to select, for a given input variable in the predefined range, one of the plurality of binary multipliers in dependence on the determined break points.

A method of manufacturing a binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments by:

• fitting, by a processor, a plurality of linear segments to the function over the predefined range, each segment extending between a pair of break points and having a fixed gradient selected from a predetermined set of fixed gradients,
• determining a base value for each of the segments;
• deriving, by a processor, a hardware representation for said binary logic circuit which includes:
• for each of the plurality of linear segments:
• a binary multiplier adapted to perform multiplication by the selected fixed gradient of the segment using h−1 binary adders, where h is the minimum Hamming weight of:
• a binary representation of the fixed gradient;
• a trinary representation of the fixed gradient;
• and
• a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary number;
• wherein the h−1 binary adders are logically configured to perform multiplication using the representation of the fixed gradient having the minimum Hamming weight h;
• and
• a binary adder adapted to add the determined base value to the input or output of the binary multiplier;
• and
• selection logic adapted to select, for a given input variable in the predefined range, one of the plurality of binary multipliers in dependence on the determined break points;
• and
• assembling said binary logic circuit in accordance with said hardware representation.