Apparatus, method and system for memory device access with a multi-cycle command
AssigneeIntel Corporation
InventorKuljit S. BAINS
Life of this patent
Estimating the term…
Abstract
Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command.
Claims25
A memory device comprising:
- detector logic to detect an exchange of a first multi-cycle command from a memory controller to the memory device, the first multi-cycle command indicating an access to a first bank of the memory device;
- control logic including circuitry configured to time, based on the detected exchange, an assertion of a second command during one or more cycles of a clock signal, the second command to perform one of an activation of the first bank and a refresh of the first bank, including the control logic to time a last cycle of the second command to begin during or after an expiration of a period of time from a beginning of a last cycle of the first multi-cycle command, wherein the period of time is equal to a predefined row precharge time delay parameter.
A memory controller comprising:
- command logic to exchange a first multi-cycle command from the memory controller to a memory device, the first multi-cycle command indicating an access to a first bank of the memory device;
- timer logic to time, based on the detected exchange, a transmission of a second command to the memory device during one or more cycles of a clock signal, the second command to perform one of an activation of the first bank and a refresh of the first bank, including the timer logic to time a last cycle of the second command to begin during or after an expiration of a period of time from a beginning of a last cycle of the first multi-cycle command, wherein the period of time is equal to a predefined row precharge time delay parameter.
A method comprising:
- detecting an exchange of a first multi-cycle command from a memory controller to a memory device, the first multi-cycle command indicating an access to a first bank of the memory device;
- based on the detected exchange, timing an assertion of a second command during one or more cycles of a clock signal, the second command to perform one of an activation of the first bank and a refresh of the first bank, including timing a last cycle of the second command to begin during or after an expiration of a period of time from a beginning of a last cycle of the first multi-cycle command, wherein the period of time is equal to a predefined row precharge time delay parameter.
Dependencies are inferred from the claim text.