Graphics display system with unified memory architecture

A memory system comprising:

• a memory that is shared by a plurality of devices;
• a first memory controller;
• a second memory controller;
• a memory request arbiter coupled to the memory, wherein the memory request arbiter is configured to perform real time scheduling of memory requests from different devices having different priorities and provides access to the memory by the plurality of devices, the memory request arbiter comprising a first arbiter coupled to the first memory controller and a second arbiter coupled to the second memory controller;
• and
• a memory select circuit configured to:
• receive the memory requests from the plurality of devices;
• and
• for each of the memory requests, select one of the first arbiter or the second arbiter using a characteristic of the memory request and provide the memory request to the selected one of the first arbiter or the second arbiter;
• wherein the memory system is configured to enforce a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.

A method comprising:

• receiving a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;
• for each of the memory requests, selecting one of a first arbiter or a second arbiter using a characteristic of the memory request;
• for each of the memory requests, providing the memory request to the selected one of the first arbiter or the second arbiter;
• performing scheduling of the memory requests using the first arbiter and the second arbiter;
• and
• enforcing a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.

A memory system comprising:

• circuitry configured to:
• receive a plurality of memory requests from a plurality of devices for access to a memory shared by the plurality of devices, the plurality of memory requests having different priorities;
• for each of the memory requests, select one of a first arbiter or a second arbiter using a characteristic of the memory request, the first arbiter and the second arbiter implemented within the circuitry;
• for each of the memory requests, provide the memory request to the selected one of the first arbiter or the second arbiter;
• perform scheduling of the memory requests using the first arbiter and the second arbiter;
• and
• enforce a minimum interval between accesses of the memory, the minimum interval configured to prevent a first device of the plurality of devices from accessing the memory during consecutive memory cycles when a second device of the plurality of devices is also requesting access to the memory.