Apparatus including memory system controllers and related methods
AssigneeMicron Technology, Inc.
InventorA. Kent Porterfield
Life of this patent
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Abstract
Memory system controllers can include non-volatile memory control circuitry including a plurality of channel control circuits. Each of the plurality of channel control circuits can be configured to be coupled to a respective number of logical units (LUNs). Memory management circuitry can be coupled to the non-volatile memory control circuitry and configured to allocate a write block cluster for host writes based on an information width of a host bus and a protocol of the host bus. The write block cluster can include one block from fewer than all of the LUNs.
Claims21
1-20. (canceled)
An apparatus, comprising:
- non-volatile memory control circuitry including a plurality of channel control circuits, wherein each of the plurality of channel control circuits is configured to be coupled to a respective number of logical units (LUNs) that each include a plurality of blocks;
- and
- memory management circuitry coupled to the non-volatile memory control circuitry and configured to:
- allocate a write block cluster for host writes such that blocks of the write block cluster are written in a particular sequence of LUNs, wherein the write block cluster is based on an information width of a host bus and a protocol of the host bus, and wherein the write block cluster comprises one of the plurality of blocks from fewer than all of the LUNs;
- and
- allocate a remainder of the plurality of blocks from the LUNs for wear leveling operations.
A method, comprising:
- allocating a write block cluster via memory management control circuitry for host writes such that a plurality of blocks of the write block cluster are written in a particular sequence of a plurality of logical units (LUNs), wherein the write block cluster is based on an information width of a host bus and a protocol of the host bus, and wherein the write block cluster comprises one block from fewer than all of the plurality of LUNs;
- and
- allocating a remainder of the plurality of blocks from the plurality of LUNs for wear leveling operations;
- wherein each of a plurality of channel control circuits is configured to be coupled to a respective number of the plurality of LUNs.
A method, comprising:
- allocating a write block cluster via memory management control circuitry for host writes such that blocks of the write block cluster are written in a particular sequence of a plurality of logical units (LUNs), wherein the write block cluster is based on an information width of a host bus and a protocol of the host bus, and wherein the write block cluster comprises one block from fewer than all of the plurality of LUNs that each include a plurality of blocks;
- and
- allocating a remainder of the plurality of blocks from the plurality of LUNs for wear leveling operations via the memory management control circuitry.
Dependencies are inferred from the claim text.