Fast-wake memory control
AssigneeRambus Inc.
InventorsFrederick A. Ware, Jared L. Zerbe, Brian S. Leibowitz
Life of this patent
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Abstract
A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.
Claims20
A method of operation within a memory controller, the method comprising:
- transitioning to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency of the memory controller is disabled;
- and
- transmitting a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.
A memory controller comprising:
- first command signaling circuitry to transmit memory access commands to a memory device at a first command-signaling frequency of the memory controller;
- power-state logic to transition the memory controller to a first power mode in which at least part of the first command signaling circuitry is disabled;
- and
- second command signaling circuitry to transmit at least one memory access command to the memory device during a transitional interval in which the at least part of the first command signaling circuitry is re-enabled.
A non-transitory computer readable medium that stores data representative of an integrated-circuit memory controller comprising:
- first command signaling circuitry to transmit memory access commands to a memory device at a first command-signaling frequency of the memory controller;
- power-state logic to transition the memory controller to a first power mode in which at least part of the first command signaling circuitry is disabled;
- and
- second command signaling circuitry to transmit at least one memory access command to the memory device during a transitional interval in which the at least part of the first command signaling circuitry is re-enabled.
Dependencies are inferred from the claim text.