Chip instrumentation for in-situ clock domain characterization
AssigneeBroadcom Corporation
InventorRafael CARMON
Life of this patent
Estimating the term…
Abstract
Chip instrumentation determines, in-situ, an allowable increase over product specification in the operating frequency of at least one clock domain in an integrated circuit for a given set of environmental, power supply and/or functionality constraints. Information on the allowable increase in operating frequency for the at least one clock domain is provided to circuits and/or software to effect change in operating frequency.
Claims20
A method of providing information indicative of an operating speed for a clock domain on a chip, comprising:
- setting, on the chip, information that defines a test operating speed;
- determining that speed testing is to be initiated;
- operating, at the test operating speed, a duplicate critical circuit path;
- determining whether the duplicate critical circuit path produces an expected result when operated at the test operating speed;
- changing, if the determination is affirmative, the information that defines the test operating speed to produce an increased test operating speed that is increased by a predetermined amount;
- and
- setting, if the determination is negative, information that defines a real operating speed to be equal to the increased test operating speed minus the predetermined amount;
- wherein the duplicate critical circuit path matches the physical and electrical characteristics of an actual critical circuit path in the clock domain.
A method of providing information indicative of an operating speed for a clock domain on a field programmable gate array (FPGA), comprising:
- configuring a logic function in the FPGA, the configured logic function having a first critical circuit path;
- configuring a second critical circuit path on the FPGA;
- setting, on the FPGA, information that defines a test operating speed;
- determining that speed testing is to be initiated;
- operating, at the test operating speed, the second critical circuit path;
- determining whether the second critical circuit path produces an expected result when operated at the test operating speed;
- changing, if the determination is affirmative, the information that defines the test operating speed to produce an increased test operating speed that is increased by a predetermined amount;
- and
- setting, if the determination is negative, information that defines a real operating speed to be equal to the increased test operating speed minus the predetermined amount;
- wherein the second critical circuit path is a duplicate of the first critical circuit path.
A method of providing first information indicative of an operating speed for a clock domain on a chip, and providing a history of operating speeds indicative of a reliability of the chip, comprising:
- setting, on the chip, information that defines a test operating speed;
- operating, at the test operating speed, a duplicate critical circuit path;
- determining whether the duplicate critical circuit path produces an expected result when operated at the test operating speed;
- changing, if the determination is affirmative, the information that defines the test operating speed to produce an increased test operating speed that is increased by a predetermined amount;
- storing, if the determination is negative, information that defines a real operating speed to be equal to the increased test operating speed minus the predetermined amount;
- and
- creating a history of real operating speeds by repeating the steps of setting, operating, determining, changing, and storing;
- wherein the duplicate critical circuit path matches the physical and electrical characteristics of an actual critical circuit path in the clock domain.
Dependencies are inferred from the claim text.