Multi-bank digital stimulus response in a single field programmable gate array

An apparatus for moving data generated by a device under test (DUT) responsive to stimulus data to a memory, the apparatus comprising:

• a plurality of response banks, each of the response banks comprising
• an I/O bank configured to deserialize the data generated by the DUT into internal data;
• a response data manager configured to compare the internal data from the I/O bank with expected levels of the internal data to generate comparison results, and write the comparison results and tags identifying the comparison results into a FIFO register;
• and
• a response data sequencer configured to write the comparison results and the tags from the FIFO register into the memory as response data of the DUT, responsive to instructions fetched from the memory,
• wherein the response banks are configured to write the response data into the memory in a first mode responsive to the data provided as respective independent banks of channels of serial data from the DUT, and in a second mode responsive to the data provided as a combined single bank of channels of serial data from the DUT.

An apparatus for moving stimulus data and response data between a memory and a device under test (DUT), the apparatus comprising:

• a plurality of data transfer banks, each of the data transfer banks comprising
• a stimulus data sequencer configured to successively read waveform segments of complex waveforms stored in the memory and write the waveform segments into a first FIFO register responsive to instructions fetched from the memory;
• a cyclizer configured to manage the waveform segments from the first FIFO register to form waveform patterns responsive to symbols embedded within the waveform segments;
• an input/output (I/O) bank configured to convert the waveform patterns into serial data, to output the serial data as stimulus data, and to deserialize data generated by the DUT into internal data;
• a response data manager configured to compare the internal data from the I/O bank with expected levels of the internal data provided from the cyclizer to generate comparison results, and write the comparison results and tags identifying the comparison results into a second FIFO register;
• and
• a response data sequencer configured to write the comparison results and the tags from the second FIFO register into the memory as response data of the DUT, responsive to instructions fetched from the memory.