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US 2015/0316588 A1Published application
Method and Apparatus for Current-Output Peak Detection
AssigneeBrookhaven Science Associates, LLC
InventorGianluigi De Geronimo
Life of this patent
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Abstract
A method and apparatus for a current-output peak detector. A current-output peak detector circuit is disclosed and works in two phases. The peak detector circuit includes switches to switch the peak detector circuit from the first phase to the second phase upon detection of the peak voltage of an input voltage signal. The peak detector generates a current output with a high degree of accuracy in the second phase.
Claims16
A peak detector circuit generating a current output, comprising:
- an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal being coupled with an input voltage signal through a first switch, the negative input terminal being coupled with a first resistor, and the output terminal being coupled with a gate of a hold transistor MH through a second switch, a drain of the hold transistor MH being coupled with a first terminal of a hold capacitor;
- a first transistor MR1, a gate of the first transistor MR1 being coupled with the drain of the hold transistor MH and a gate of a second transistor, a drain of the first transistor MR1 being coupled with the negative input terminal of the amplifier, wherein the second transistor comprises n1 copies of the first transistor MR1 coupled in parallel and n1 is an integer;
- a third transistor MR2, a drain of the third transistor MR2 being coupled with the positive input terminal of the amplifier through a third switch and with a second resistor, the gate of the third transistor MR2 being coupled with the output terminal of the amplifier through a fourth switch and with a gate of a fourth transistor, wherein the third transistor MR2 is a copy of the first transistor MR1, a resistance value of the second resistor is equal to a resistance value of the first resistor, the fourth transistor comprises n2 copies of the third transistor MR2 coupled in parallel, and n2 is an integer;
- a fifth switch connected in parallel with the hold capacitor;
- wherein sources of the first, second, third and fourth transistors are coupled to a supply voltage, and a second terminal of the hold capacitor is coupled to the supply voltage;
- wherein the first switch, the second switch and the fifth switch are turned on, and the third and fourth switches are turned off;
- wherein the fifth switch is turned off upon receipt of the input voltage signal at the positive input terminal of the amplifier;
- wherein the first switch and the second switch are turned off, and the third and fourth switches are turned on upon detection of a peak voltage of the input voltage signal;
- and
- wherein the peak detector generates the current output at a drain of the fourth transistor corresponding to a peak voltage amplitude of the input voltage signal.
7 more elements
A circuit for processing a voltage signal, comprising:
- a charge amplifier for amplifying the voltage signal;
- a filter, coupled with the charge amplifier, receiving and filtering the amplified voltage signal and generating a filtered signal;
- and
- a peak detector coupled with the filter at an output terminal of the filter,
- generating a current output corresponding to a peak voltage amplitude of the voltage signal, the peak detector comprising:
- an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal being coupled with the filtered signal through a first switch, the negative input terminal being coupled with a first resistor, and the output terminal being coupled with a gate of a hold transistor MH through a second switch, a drain of the hold transistor being coupled with a first terminal of a hold capacitor;
- a first transistor MR1, a gate of the first transistor MR1 being coupled with the drain of the hold transistor MH and a gate of a second transistor, a drain of the first transistor MR1 being coupled with the negative input terminal of the amplifier, wherein the second transistor comprise n1 copies of the first transistor MR1 connected in parallel and n1 is an integer;
- and
- a third transistor MR2, a drain of the third transistor MR2 being coupled with the positive input terminal of the amplifier through a third switch and with a second resistor, the gate of the third transistor MR2 being coupled with the output terminal of the amplifier through a fourth switch and with a gate of a fourth transistor, wherein a resistance value of the second resistor is equal to a resistance value of the first resistor, the third transistor MR2 is a copy of the first transistor MR1, the fourth transistor comprises n2 copies of the third transistor MR2 connected in parallel, and n2 is an integer.
6 more elements
A peak detector circuit generating a current output, comprising:
- an amplifier having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal being coupled with an input voltage signal through a first switch, the negative input terminal being coupled with a first resistor, and the output terminal being coupled with a gate of a hold transistor MH through a second switch, a drain of the hold transistor MH being coupled with a first terminal of a hold capacitor;
- a first transistor MR1, a gate of the first transistor MR1 being coupled with the drain of the hold transistor MH and a gate of a second transistor, a drain of the first transistor MR1 being coupled with the negative input terminal of the amplifier, wherein the second transistor comprises n1 copies of the first transistor MR1 connected in parallel and n1 is an integer;
- and
- a reset switch connected in parallel with the hold capacitor;
- wherein sources of the first and second transistors and a second terminal of the hold capacitor are coupled to a supply voltage.
2 more elements
Dependencies are inferred from the claim text.