Mirroring log data

A system for mirroring a caching log data structure from a primary storage controller to a secondary storage controller over multiple interconnect paths, comprising:

• a mapping component configured to:
• parse a caching log data structure of a primary storage controller into a first stream and a second stream;
• assign the first stream to a first interconnect path between the primary storage controller and a secondary storage controller;
• assign the second stream to a second interconnect path between the primary storage controller and the secondary storage controller;
• enforce a data ordering rule during mirroring of first storage information of the first stream from a primary write cache of the primary storage controller to a secondary write cache of the secondary storage controller over the first interconnect path;
• and
• enforce the data ordering rule during mirroring of second storage information of the second stream from the primary write cache to the secondary write cache over the second interconnect path.

A computer readable medium comprising instructions that when executed perform a method for mirroring a caching log data structure from a primary storage controller to a secondary storage controller over multiple interconnect paths, comprising:

• parsing a caching log data structure of a primary storage controller into a first stream and a second stream;
• assigning the first stream to a first interconnect path between the primary storage controller and a secondary storage controller;
• assigning the second stream to a second interconnect path between the primary storage controller and the secondary storage controller;
• enforcing a data ordering rule during mirroring of first storage information of the first stream from a primary write cache of the primary storage controller to a secondary write cache of the secondary storage controller over the first interconnect path;
• and
• enforcing the data ordering rule during mirroring of second storage information of the second stream from the primary write cache to the secondary write cache over the second interconnect path.