Simplified and Effective Offset Calibration Circuit for RxLOS in Serdes
AssigneeLSI Corporation
InventorsShu Dong Cheng, Ming Chen, Yan Xu, Dong Hui Wang, Jun Tian
Life of this patent
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Abstract
A method for offset cancellation in a receiver loss of signal (RxLOS) circuit of a serializer/deserializer (SerDes) receiver device includes receiving a differential input signal via the first stage of a peak detector cell of the RxLOS circuit and shorting the differential output of the first stage via a control switch of the second stage of the RxLOS circuit. The control switch may further transition the RxLOS circuit from normal operating mode to an offset cancellation mode wherein the control switch may manually or automatically short the differential output of the first stage.
Claims19
A method for cancelling offset in a differential signal via a receiver loss of signal (RxLOS) circuit, the method comprising:
- switching the receiver loss of signal circuit from an operating mode to an offset calibration mode;
- receiving a differential input signal;
- generating a first differential output signal;
- shorting the first differential output signal to generate at least a second differential output signal and a common mode voltage;
- and
- switching the receiver loss of signal circuit from the offset calibration mode to the operating mode.
A peak detector cell, comprising:
- a first stage including circuitry configured to receive at least one differential input signal and to generate at least one first differential output signal;
- a second stage including at least one control switch configured to short the at least one first differential output signal and to generate at least a second differential output signal and a common mode voltage;
- and
- a third stage including circuitry configured to receive the at least one second differential output signal and to generate at least one third differential output signal.
A serializer-deserializer (SerDes) receiver device including receiver loss of signal (RxLOS) circuitry, the circuitry comprising:
- a first stage including circuitry configured to receive at least one differential input signal and generate at least one first differential output signal;
- a second stage including at least one control switch configured to short the at least one first differential output signal and generate at least one of a second differential output signal and a common mode voltage;
- and
- a third stage including circuitry configured to receive the at least one second differential output signal and generate at least one third differential output signal.
Dependencies are inferred from the claim text.