US 2015/0311905 A1 · ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL)

Abstract

An all-digital phase-locked loop (ADPLL) is provided. The ADPLL comprises a first circuit and a second circuit. The first circuit is configured to monitor a first signal and set a voltage of a second signal to a voltage within a first voltage range when a code of fine-tuning is equal to a first specified value. The first circuit is configured to set a voltage of a third signal to a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value. The second circuit is configured to increase a code of coarse-tuning when the voltage of the second signal is within the first voltage range, and decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range. The ADPLL provides a target frequency despite changes in at least one of process, voltage or temperature.

Claims20

Dependent claims

An all-digital phase-locked loop (ADPLL), comprising:

a first circuit, configured to:
monitor a first signal, the first signal comprising a code of fine-tuning;
output a second signal, the second signal having a voltage within a first voltage range when the code of fine-tuning is equal to a first specified value;
and
output a third signal, the third signal having a voltage within a second voltage range when the code of fine-tuning is equal to a second specified value;
and
a second circuit, configured to:
output a fourth signal, the fourth signal comprising a code of coarse-tuning;
increase the code of coarse-tuning when the voltage of the second signal is within the first voltage range;
and
decrease of the code of coarse-tuning when the voltage of the third signal is within the second voltage range.

8 more elements

An all-digital phase-locked loop (ADPLL), comprising:

a first circuit, configured to:
monitor a first signal, the first signal comprising a code of fine-tuning;
detect when the code of fine-tuning is equal to a first specified value;
detect when the code of fine-tuning is equal to a second specified value;
output a second signal, the second signal having a voltage within a first voltage range when the code of fine-tuning is equal to the first specified value;
and
output a third signal, the third signal having a voltage within a second voltage range when the code of fine-tuning is equal to the second specified value;
a logic gate, configured to:
receive the second signal;
receive the third signal;
and
output a fifth signal based upon the second signal and the third signal;
a third circuit, configured to:
receive a sixth signal;
receive a reference frequency signal;
and
output a frequency divider signal;
a fourth circuit, configured to:
monitor a fourth signal, the fourth signal comprising a code of coarse-tuning;
detect when the code of coarse-tuning is equal to a third specified value;
detect when the code of coarse-tuning is equal to a fourth specified value;
and
output an eighth signal, the eighth signal having a voltage within a third voltage range when the code of coarse-tuning is equal to the third specified value and when the code of coarse-tuning is equal to the fourth specified value;
and
a second circuit, configured to:
receive the frequency divider signal;
receive the second signal;
receive the third signal;
receive a seventh signal;
and
output the fourth signal based upon the frequency divider signal, the second signal, the third signal and the seventh signal.

28 more elements

Dependencies are inferred from the claim text.

All-digital phase-locked loop (adpll)

Life of this patent

All-digital phase-locked loop (adpll)

Life of this patent

Abstract

Claims20