US 2015/0311904 A1 · SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Abstract

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

Claims10

Dependent claims

1-12. (canceled)

A semiconductor device comprising:

a central processing unit;
a data bus;
and
a communication controller coupled with the central processing unit via the data bus, which is configured to control communication with an interface IC,
the communication controller comprising:
a clock input buffer configured to receive an external clock signal from the interface IC;
a data input buffer configured to receive input data from the interface IC;
an input circuit configured to receive the input data from the data input buffer and output the input data to the central processing unit via the data bus;
an output circuit configured to receive output data from the central processing unit via the data bus;
a data output buffer configured to receive the output data from the output circuit and output the output data to the interface IC;
a first PLL circuit coupled with the clock input buffer and the input circuit;
a first delay circuit coupled with the first PLL circuit;
a second PLL circuit coupled with the clock input buffer and the output circuit;
and
a second delay circuit coupled with the second PLL circuit,
wherein the first delay circuit is configured to delay a first feedback signal outputted from the first PLL circuit to generate a first delay clock signal and output the first delay clock signal to the first PLL circuit,
wherein the first PLL circuit is configured to perform phase adjustment between the external clock signal and the first delay clock signal to generate a first internal clock signal,
wherein the input data is transferred from the input data buffer to the input circuit in accordance with the first internal clock signal,
wherein the second delay circuit is configured to delay a second feedback signal outputted from the second PLL circuit to generate a second delay clock signal and output the second delay clock signal to the second PLL circuit,
wherein the second PLL circuit is configured to perform phase adjustment between the external clock signal and the second delay clock signal to generate a second internal clock signal, and
wherein the output data is transferred from the output circuit to the output buffer in accordance with the second internal clock signal.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/735,563Filed 10 Jun 2015

Priority

JP 2012-17842610 Aug 2012

Published

29 Oct 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H03L 7/08
Using a reference signal applied to a frequency- or phase-locked loop: details of the phase-locked loop
G06F 1/10
Generating or distributing clock signals or signals derived directly therefrom: distribution of clock signals , e.g. skew
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…
H03L 7/18
Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop:…

Semiconductor device and electronic device

Life of this patent

Semiconductor device and electronic device

Life of this patent

Abstract

Claims10