Method, apparatus and system for an edge rate controlled output buffer
AssigneeTexas Instruments Incorporated
InventorsByungchul B. Jang, Timothy B. Merkin
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Abstract
A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.
Claims6
A circuit for minimizing variation over process, voltage and temperature for edge rate over and signal independent propagation delay, comprising:
- at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers;
- at least two second buffers for level shifting to the at least two first buffers;
- and
- at least two voltage sources for initializing the stage of at least one of the first or the second buffer;
- and
- a current source generator coupled to the voltage source of the second buffers.
A system for controlling the edge rate of output signals to eliminate any high order of harmonics to reduce EMI/EMC emission comprising a circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay, the circuit comprises:
- at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers;
- at least two second buffers for level shifting to the at least two first buffers;
- and
- at least two voltage sources for initializing the stage of at least one of the first or the second buffer;
- and
- a current source generator coupled to the voltage source of the second buffers.
Dependencies are inferred from the claim text.