US 2015/0311337 A1 · FINFET DEVICE COMPRISING A THERMAL OXIDE REGION POSITIONED BETWEEN A PORTION OF THE FIN AND A LAYER OF INSULATING MATERIAL

Abstract

Disclosed herein are various methods of forming isolation structures on FinFETs and other semiconductor devices, and the resulting devices that have such isolation structures. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define a fin for a FinFET device, forming a layer of insulating material in the trenches, wherein the layer of insulating material covers a lower portion of the fin but not an upper portion of the fin, forming a protective material on the upper portion of the fin, and performing a heating process in an oxidizing ambient to form a thermal oxide region on the covered lower portion of the fin.

Claims16

Dependent claims

-19. (canceled)

Dependencies are inferred from the claim text.

Facts

Application

14/792,742Filed 7 Jul 2015

Priority

16 Jan 2012

Published

29 Oct 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Finfet device comprising a thermal oxide region positioned between a portion of the fin and a layer of insulating material

Life of this patent

Finfet device comprising a thermal oxide region positioned between a portion of the fin and a layer of insulating material

Life of this patent

Abstract

Claims16