Fet transistor on a iii-v material structure with substrate transfer
AssigneeHRL Laboratories, LLC
InventorsZijian "Ray" LI, Rongming CHU
Life of this patent
Estimating the term…
Loading patent…
AssigneeHRL Laboratories, LLC
InventorsZijian "Ray" LI, Rongming CHU
Estimating the term…
A method of manufacturing a III-V semiconductor circuit; the method comprising: forming a first layer of a III-V material on a growth substrate; forming a second layer of a III-V material on the first layer of III-V material; forming a FET transistor having a source electrode and a drain electrode in contact with a top surface of the second layer of a III-V material; forming a top dielectric layer above the FET transistor; forming a metal layer above the top dielectric layer, wherein said metal layer is connected to said source electrode; attaching a handle substrate to a top surface of the metal layer; removing the growth substrate from the bottom of the first layer of a III-V material; and forming a bottom dielectric layer on the bottom of the first layer of a III-V material.
A semiconductor circuit comprising a III-V material structure attached to a handle substrate by a metal layer, wherein
A method of manufacturing a III-V semiconductor circuit;
Dependencies are inferred from the claim text.