US 2015/0311323 A1 · SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Claims16

Dependent claims

(canceled)

A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;
implanting oxygen ions into the oxide semiconductor layer;
performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;
performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer;
wherein the second heat treatment is performed after the first heat treatment.

2 more elements

A method for manufacturing a semiconductor device, comprising the steps of:

forming an oxide semiconductor layer over an insulating surface, the oxide semiconductor layer including a channel formation region, the oxide semiconductor layer containing indium, tin and zinc;
implanting oxygen ions into the oxide semiconductor layer;
performing a first heat treatment on the oxide semiconductor layer in an atmosphere containing nitrogen;
performing a second heat treatment on the oxide semiconductor layer in an atmosphere containing oxygen so that the oxide semiconductor layer includes excess oxygen and the oxide semiconductor layer is capable of compensating an oxygen deficiency in the oxide semiconductor layer;
and
performing a oxygen doping into the oxide semiconductor layer,
wherein the second heat treatment is performed after the first heat treatment.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/740,688Filed 16 Jun 2015

Priority

JP 2010-1769826 Aug 2010

Published

29 Oct 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification35 codes

G11C 16/0408
Using variable threshold transistors, e.g. FAMOS: comprising cells containing floating gate transistors
G11C 11/404
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with one charge-transfer gate, e.g. MOS transistor, per cell
G11C 11/405
With charge regeneration common to a multiplicity of memory cells, i.e. external refresh: with three charge-transfer gates, e.g. MOS transistors,…
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits

Family

Application13/195,105Continuation · filed 1 Aug 2011

Application13/861,681Continuation · filed 12 Apr 2013

Application14/552,551Continuation · filed 25 Nov 2014

Application14/740,688Continuation

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