Vertical Bit Line Wide Band Gap TFT Decoder
AssigneeSanDisk 3D LLC
InventorsPeter Rabkin, Masaaki Higashitani
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Abstract
A 3D memory array having a vertically oriented thin film transistor (TFT) selection device that has a body formed from a wide energy band gap semiconductor is disclosed. The wide energy band gap semiconductor may be an oxide semiconductor, such as a metal oxide semiconductor. As examples, this could be an InGaZnO, InZnO, HfInZnO, or ZnInSnO body. The source and drains can also be formed from the wide energy band gap semiconductor, although these may be doped for better conduction. The vertically oriented TFT selection device serves as a vertical bit line selection device in the 3D memory array. A vertical TFT select device has a high drive current, a high breakdown voltage and low leakage current.
Claims20
A method for forming a non-volatile storage system, the method comprising:
- forming a three dimensional memory array of memory cells above a substrate;
- forming a plurality of word lines coupled to a subset of the memory cells;
- forming a plurality of global bit lines;
- forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate;
- and
- forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
- wherein forming each of the vertically oriented TFT select devices comprises:
- forming a first source/drain electrically coupled to a first global bit line of the global bit lines;
- forming a body that includes a wide band gap semiconductor having an energy band gap greater than 1.1 eV;
- forming a second source/drain electrically coupled to a first vertical bit line of the vertical bit lines;
- forming a gate;
- and
- forming a gate dielectric between the gate and the body.
A method for forming a non-volatile storage system, the method comprising:
- forming a three dimensional memory array of ReRAM memory cells above a substrate;
- forming a plurality of word lines coupled to a subset of the ReRAM memory cells;
- forming a plurality of global bit lines;
- forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate;
- and
- forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
- wherein forming each of the vertically oriented TFT select devices comprises:
- forming a first source/drain that is an oxide semiconductor and that is electrically coupled to a first global bit line of the global bit lines;
- forming a body that is the oxide semiconductor;
- forming a second source/drain that is the oxide semiconductor and is electrically coupled to a first vertical bit line of the vertical bit lines;
- forming a gate;
- and
- forming a gate dielectric between the gate and the body.
A method for forming a non-volatile storage system, the method comprising:
- forming a three dimensional memory array of ReRAM memory cells above a substrate;
- forming a plurality of word lines coupled to a subset of the ReRAM memory cells;
- forming a plurality of global bit lines;
- forming a plurality of vertically oriented bit lines coupled to the memory cells, wherein the vertically oriented bit lines are oriented vertically with respect to the substrate;
- and
- forming a plurality of vertically oriented thin film transistor (TFT) select devices, wherein the vertically oriented TFT select devices are oriented vertically with respect to the substrate;
- wherein forming each of the vertically oriented TFT select devices comprises:
- forming a first source/drain that is a metal and that is electrically coupled to a first global bit line of the global bit lines;
- forming a body that is an oxide semiconductor that is in direct contact with the metal of the first source/drain;
- forming a second source/drain that is a metal that is in direct contact with the oxide semiconductor of the body and is electrically coupled to a first vertical bit line of the vertical bit lines;
- forming a gate;
- and
- forming a gate dielectric between the gate and the body.
Dependencies are inferred from the claim text.