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US 2015/0311218 A1Published application
Method of Shaping Densely Arranged PL Gates and Peripheral MOS Gates for ILD Oxide Fill-In
AssigneeMacronix International Co., Ltd.
InventorsFang-Hao Hsu, Shih-Ping Hong, Hong-Ji Lee
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Abstract
A method is described that facilitates inter-layer dielectric fill-in among transistors in a densely-configured array of an integrated circuit. An etch process that exploits a micro-loading effect to create a T-shaped profile between transistors is disclosed. The micro-loading has a negligible effect on transistors in a peripheral region of the integrated circuit.
Claims20
A semiconductor device comprising:
- a substrate;
- a plurality of first stacked structures arranged on the substrate in a densely arranged region;
- and
- a plurality of second stacked structures arranged on the substrate in a peripheral area, wherein each of the first and second stack structures comprises:
- a first dielectric layer overlying the substrate;
- a first polysilicon layer overlying the first dielectric layer;
- a second dielectric layer overlying the first polysilicon layer;
- a second polysilicon layer overlying the second dielectric layer;
- and
- a metal silicide layer overlying the second dielectric layer, wherein the second dielectric layer exhibits a profile shape substantially as a trapezoid.
7 more elements
A method of semiconductor manufacture, comprising:
- forming a plurality of polysilicon layers above a substrate, the layers being separated from the substrate and from each other by insulating layers;
- depositing a conducting layer above the plurality of polysilicon layers;
- and
- etching to form a plurality of polysilicon gates having T-shaped profiles therebetween in a densely arranged array of gate structures and smooth profiles in peripheral structures.
1 more element
Dependencies are inferred from the claim text.