Otp memory
AssigneeRenesas Electronics Corporation
InventorsKenichi HIDAKA, Yoshitaka KUBOTA
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Abstract
The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.
Claims2
A memory cell for an OTP (One Time Programmable) memory, comprising:
- a first Metal-Insulator-Semiconductor (MIS) transistor comprising a first source region, a first drain region and a first gate;
- and forming a first current path between the first source region and the first drain region in accordance with voltage applied to the first;
- a second MIS transistor comprising a second source region, a second drain region and a second gate, and forming a second current path between the second source region and the second drain region in accordance with voltage applied to the second gate, the source region being coupled to the first gate of the memory transistor via a first line;
- and
- a capacitor comprising a first electrode and a second electrode, the first electrode coupled to the first source region.
Dependencies are inferred from the claim text.