Methods of manufacturing a semiconductor device

A vertical memory device, comprising:

• a pillar structure on a substrate, the pillar structure including a channel pattern extending in a vertical direction from a top surface of the substrate;
• a plurality of conductive layer patterns surrounding outer sidewalls of the pillar structure, the conductive layer patterns stacked in the vertical direction to be spaced apart from each other, each of the conductive layer patterns extending in a first direction substantially parallel to the top surface of the substrate;
• and
• a lower sacrificial layer pattern on the substrate, the lower sacrificial layer pattern and a sidewall in the first direction of a lowermost conductive layer pattern of the conductive layer patterns being spaced apart from each other and facing each other.

A vertical memory device, comprising:

• a pillar structure on a first region of a substrate, the pillar structure including a channel pattern extending in a vertical direction from a top surface of the substrate;
• a plurality of conductive layer patterns surrounding outer sidewalls of the pillar structure, the conductive layer patterns stacked in the vertical direction to be spaced apart from each other, each of the conductive layer patterns extending in a first direction substantially parallel to the top surface of the substrate;
• a transistor on a second region of the substrate, the transistor including a gate structure;
• and
• an etch stopping layer on the gate structure in the second region of the substrate, the etch stopping layer having a thickness substantially the same as a thickness of a lowermost conductive layer pattern of the conductive layer patterns.