Methods of forming gate structures for transistor devices for cmos applications and the resulting products

An integrated circuit product, comprising:

• an NMOS transistor, said NMOS transistor comprising:
• an NMOS gate structure, comprising:
• an NMOS gate insulation layer comprised of a high-k gate insulation material;
• a first NMOS metal layer comprised of a first metal positioned on said NMOS gate insulation layer;
• and
• an NMOS metal silicide material positioned above said first NMOS metal layer, said NMOS metal silicide material comprising a first amount of atomic silicon;
• a first dielectric gate cap layer positioned above said NMOS gate structure;
• and
• a first sidewall spacer positioned adjacent to and laterally confining sidewalls of said NMOS gate structure and sidewalls of said first dielectric gate cap layer;
• and
• a PMOS transistor, said PMOS transistor comprising:
• a PMOS gate structure, comprising:
• a PMOS gate insulation layer comprised of said high-k gate insulation material;
• a first PMOS metal layer comprised of said first metal positioned on said PMOS gate insulation layer;
• and
• a PMOS metal silicide material positioned above said first PMOS metal layer, said PMOS metal silicide material comprising a second amount of atomic silicon, wherein said first and second amounts of atomic silicon are different;
• a second dielectric gate cap layer positioned above said PMOS gate structure;
• and
• a second sidewall spacer positioned adjacent to and laterally confining sidewalls of said PMOS gate structure and sidewalls of said second dielectric gate cap layer.

An integrated circuit product, comprising:

• an NMOS transistor having an NMOS gate structure comprised of:
• an NMOS gate insulation layer comprised of a high-k gate insulation material;
• a first NMOS metal layer comprised of a first metal material positioned on said NMOS gate insulation layer;
• an NMOS metal silicide material positioned above said first NMOS metal layer, said NMOS metal silicide material comprising 50-95% atomic silicon;
• and
• a layer of a second metal material positioned above and in contact with each of said NMOS gate insulation layer, said first NMOS metal layer, and said NMOS metal silicide layer;
• and
• a PMOS transistor having a PMOS gate structure comprised of:
• a PMOS gate insulation layer comprised of said high-k gate insulation material;
• a first PMOS metal layer comprised of said first metal material positioned on said PMOS gate insulation layer;
• a PMOS metal silicide material positioned above said first PMOS metal layer, said PMOS metal silicide material comprising 2-40% atomic silicon;
• and
• a layer of said second metal material positioned above and in contact with each of said PMOS gate insulation layer, said first PMOS metal layer, and said PMOS metal silicide layer.

An integrated circuit product, comprising:

• an NMOS transistor, said NMOS transistor comprising:
• an NMOS gate structure, comprising:
• an NMOS gate insulation layer comprised of a high-k gate insulation material, wherein said NMOS gate insulation layer comprises a first horizontal bottom portion positioned above an active region of said NMOS transistor and first vertical sidewall portions that define a portion of a sidewall of said NMOS gate structure;
• a first NMOS metal layer comprised of a first metal material positioned on said NMOS gate insulation layer;
• and
• an NMOS metal silicide material positioned above said first NMOS metal layer, said NMOS metal silicide material comprising a first amount of atomic silicon, wherein said first vertical sidewall portions of said NMOS gate insulation layer laterally confine said first NMOS metal layer and said NMOS metal silicide material;
• a first dielectric gate cap layer positioned above said NMOS gate structure;
• and
• a first sidewall spacer positioned adjacent to and laterally confining sidewalls of said NMOS gate structure and sidewalls of said first dielectric gate cap layer;
• and
• a PMOS transistor, said PMOS transistor comprising:
• a PMOS gate structure, comprising:
• a PMOS gate insulation layer comprised of said high-k gate insulation material, wherein said PMOS gate insulation layer comprises a second horizontal bottom portion positioned above an active region of said PMOS transistor and second vertical sidewall portions that define a portion of a sidewall of said PMOS gate structure;
• a first PMOS metal layer comprised of said first metal material positioned on said PMOS gate insulation layer;
• and
• a PMOS metal silicide material positioned above said first PMOS metal layer, said PMOS metal silicide material comprising a second amount of atomic silicon that is different from said first amount of atomic silicon, wherein said second vertical sidewall portions of said PMOS gate insulation layer laterally confine said first PMOS metal layer and said PMOS metal silicide material;
• a second dielectric gate cap layer positioned above said PMOS gate structure;
• and
• a second sidewall spacer positioned adjacent to and laterally confining sidewalls of said PMOS gate structure and sidewalls of said second dielectric gate cap layer.