Semiconductor device with metal gate
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsDa-Yuan Lee, Kuang-Yuan Hsu
Life of this patent
Estimating the term…
Abstract
A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer, an etch stop layer, a first work function metal, a second work function metal, and a fill metal. A second gate structure is also disposed on the semiconductor substrate. The second gate structure includes the gate dielectric layer, a second work function metal, and the fill metal. In an embodiment, the second gate structure also includes an etch stop layer.
Claims20
A semiconductor device, comprising:
- a first gate structure formed on a semiconductor substrate, wherein the first gate structure includes a gate dielectric layer, an etch stop layer between the gate dielectric layer and a first work function metal layer, a second work function metal on the first work function metal layer, and a fill metal layer;
- and
- a second gate structure formed on the semiconductor device, wherein the second gate structure includes the gate dielectric layer, the second work function metal on the gate dielectric layer, and the fill metal.
A device, comprising:
- a PMOS gate structure including:
- a gate dielectric layer;
- an etch stop layer on the gate dielectric layer;
- a p-type work function layer directly on the etch stop layer;
- an n-type work function layer on the p-type work function layer;
- and
- an NMOS gate structure including:
- the gate dielectric layer;
- and
- the n-type work function layer directly on the gate dielectric layer.
A device, comprising:
- a first gate structure of a first type including:
- a high-k gate dielectric layer;
- an etch stop layer on the gate dielectric layer, wherein the etch stop layer includes a mid-gap metal;
- a first-type work function layer interfacing the etch stop layer;
- and
- a second gate structure of a second type including:
- the high-k gate dielectric layer;
- and
- a second-type work function layer interfacing the gate dielectric layer, wherein the second-type work function layer is one of an n-type work function and a p-type work function and the first type work function layer is the other one of the n-type work function and the p-type work function.
Dependencies are inferred from the claim text.