Back to results
US 2015/0311198 A1Published application
System and method of varying gate lengths of multiple cores
AssigneeQUALCOMM Incorporated
InventorsMing Cai, Samit Sengupta, Chock Hing Gan, PR Chidambaram
Life of this patent
Estimating the term…
Abstract
A method includes forming a first gate of a first transistor, the first gate having a first length. The first transistor is located in a first core. The method also includes forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length. The second transistor is located in a second core. The first core is located closer to a center of a semiconductor die than the second core. The second transistor and the first transistor are corresponding transistors.
Claims30
A method comprising:
- forming a first gate of a first transistor, the first gate having a first length, wherein the first transistor is located in a first core;
- and
- forming a second gate of a second transistor, the second gate having a second length that is shorter than the first length, wherein the second transistor is located in a second core, and wherein the first core is located closer to a center of a semiconductor die as compared to the second core, wherein the second transistor and the first transistor are corresponding transistors.
An apparatus comprising:
- a first core that includes a first transistor, wherein the first transistor includes a first gate, the first gate having a first length;
- a second core that includes a second transistor, wherein the second transistor includes a second gate having a second length, wherein the first core is located closer to a center of a semiconductor die than the second core;
- and
- a third core that includes a third transistor, wherein the third transistor includes a third gate having a third length that is different than the first length, wherein the third core is located in a second semiconductor die.
1 more element
An apparatus comprising:
- first means for processing, wherein the first means for processing includes a first transistor, wherein the first transistor includes a first gate, the first gate having a first length;
- and
- second means for processing, wherein the second means for processing includes a second transistor, wherein the second transistor includes a second gate having a second length that is shorter than the first length, wherein the first means for processing is located closer to a center of a semiconductor die than the second means for processing, and wherein the second transistor and the first transistor are corresponding transistors.
Dependencies are inferred from the claim text.