Methods of Fabrication and Testing of Three-Dimensional Stacked Integrated Circuit System-In-Package

A method of fabricating a three-dimensional (3D) stacked integrated circuit (IC) system-in-package (SiP), comprising:

• step S101:
• providing a first semiconductor wafer having a plurality of first dies formed thereon, the plurality of first dies having top surfaces located in a same plane as a top surface of the first semiconductor wafer, each of the plurality of first dies having a first wire bond pad formed in a peripheral part thereof and a first dielectric layer over the top surface thereof, wherein at least a portion of a surface of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die;
• step S102:
• providing a plurality of second dies, each having a second wire bond pad formed in a peripheral part thereof and a second dielectric layer over a top surface thereof, wherein at least a portion of a surface of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die, the exposed area of the second die being different in size compared with the exposed area of the first die;
• step S103:
• aligning each of the plurality of second dies with a corresponding one of the plurality of first dies and bonding the second dielectric layer of each of the plurality of second dies to the first dielectric layer of a corresponding one of the plurality of first dies, such that a cavity is formed in each pair of the bonded first and second dies, wherein the at least a portion of the surface of the second wire bond pad and the at least a portion of the surface of the first wire bond pad are exposed in the cavity and faces each other;
• and
• step S104:
• plating the first semiconductor wafer bonded with the plurality of second dies such that a plating structure fills the cavity of each pair of the bonded first and second dies, thereby forming plating electrical interconnects vertically interconnecting the first and second wire bond pads in the cavity.