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US 2015/0311183 A1Published application
Wafer, package structure and method of manufacturing the same
AssigneeUnited Microelectronics Corp.
InventorChien-Li Kuo
Life of this patent
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Abstract
The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
Claims20
A method of forming a package structure, comprising:
- providing an array chip comprising a plurality of first dies;
- providing a wafer comprising a plurality of second dies;
- and
- performing a package step to package the array chip correspondingly on the wafer such that each first die electrically connects each second die.
1 more element
A semiconductor wafer, comprising:
- a plurality of array regions, wherein a first gap is disposed between each array region;
- a plurality of die regions in one array region, wherein a second gap is disposed between each die region, and the first gap is greater than the second gap;
- and
- a plurality of dies, wherein each die is disposed correspondingly in each die region.
1 more element
A package structure, comprising:
- a first die and a second die, both the first die and the second die comprise:
- a first surface;
- a second surface disposed opposite to the first surface;
- and
- at least two sidewalls disposed between the first surface and the second surface;
- and
- an underfill layer covering the first surface of the first die, the first surface of the second die and at least one sidewall of the first die, wherein at least one sidewall of the first die is not covered by the underfill layer.
4 more elements
Dependencies are inferred from the claim text.