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US 2015/0311181 A1Published application
Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same
AssigneeTera Probe, Inc.
InventorShinji Wakisaka
Life of this patent
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Abstract
A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.
Claims20
A semiconductor device manufacturing method comprising:
- mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including a semiconductor substrate, an LSI formed on a surface of the semiconductor substrate, connection pads which are connected to the LSI provided on the semiconductor substrate, an insulating film formed on the semiconductor substrate and having openings in regions corresponding to the connection pads, a wiring line provided directly on the insulating film so as to connect to one of the connection pads via one of the openings of the insulating film, and a columnar electrode formed on a land of the wiring line and protruding from the surface of the semiconductor substrate;
- stacking a sealing layer on the semiconductor constructs except for top surfaces of the columnar electrodes and on the base plate, such that the sealing layer contacts side surfaces of the wiring lines and side surfaces of the semiconductor substrates;
- forming upper wiring lines on an upper surface of the sealing layer and the top surfaces of the columnar electrodes;
- and
- dicing the sealing layer after the forming of the upper wiring lines to obtain a plurality of semiconductor devices each having at least one semiconductor construct, such that the wiring line of the at least one semiconductor construct is covered by the sealing layer except for the land where the columnar electrode is formed, and at least a part of one of the upper wiring lines is formed on the sealing layer in a region outside the semiconductor construct,
- wherein the insulating film has one or more layers and comprises at least one passivation film;
- wherein the prepreg is a sheetlike semi-cured resin;
- and
- wherein stacking the sealing layer comprises laying a prepreg on the semiconductor constructs and the base plate and heating and pressurizing the prepreg towards the base plate to form the sealing layer, such that the semiconductor constructs are embedded in the sealing layer and each of the columnar electrodes penetrates through the sealing layer, whereby the top surfaces of the columnar electrodes are exposed from the upper surface of the sealing layer.
6 more elements
A semiconductor device manufacturing method comprising:
- mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including a semiconductor substrate, an LSI formed on a surface of the semiconductor substrate, connection pads connected to the LSI provided on the semiconductor substrate, an insulating film formed on the semiconductor substrate and having openings in regions corresponding to the connection pads, a wiring line provided directly on the insulating film so as to connect to one of the connection pads via one of the openings of the insulating film, and a columnar electrode formed on a land of the wiring line and protruding from the surface of the semiconductor substrate;
- stacking a sealing layer on the semiconductor constructs except for top surfaces of the columnar electrodes and on the base plate, such that the sealing layer contacts side surfaces of the wiring lines and side surfaces of the semiconductor substrates;
- forming upper wiring lines on an upper surface of the sealing layer and the top surfaces of the columnar electrodes;
- and
- dicing the sealing layer after the forming of the upper wiring lines to obtain a plurality of semiconductor devices each having at least one semiconductor construct, such that the wiring line of the at least one semiconductor construct is covered by the sealing layer except for the land where the columnar electrode is formed, and at least a part of one of the upper wiring lines is formed on the sealing layer in a region outside the semiconductor construct,
- wherein the insulating film has two or more films and comprises a passivation film and a protection film formed on the passivation film;
- wherein the prepreg is a sheetlike semi-cured resin;
- and
- wherein stacking the sealing layer comprises laying a prepreg on the semiconductor constructs and the base plate and heating and pressurizing the prepreg towards the base plate to form the sealing layer, such that the semiconductor constructs are embedded in the sealing layer and each of the columnar electrodes penetrates through the sealing layer.
6 more elements
A semiconductor device manufacturing method comprising:
- mounting a plurality of semiconductor constructs on a base plate, each of the semiconductor constructs including a semiconductor substrate, an LSI formed on a surface of the semiconductor substrate, connection pads connected to the LSI provided on the semiconductor substrate, an insulating film formed on the semiconductor substrate and having openings in regions corresponding to the connection pads, and a columnar electrode provided to protrude from the surface of the semiconductor substrate;
- stacking a sealing layer on the semiconductor constructs except for top surfaces of the columnar electrodes and on the base plate, such that the sealing layer contacts side surfaces of the semiconductor substrates;
- forming upper wiring lines directly on an upper surface of the sealing layer and the top surfaces of the columnar electrodes;
- and
- dicing the sealing layer after the forming of the upper wiring lines to obtain a plurality of semiconductor devices each having at least one semiconductor construct, such that at least a part of one of the upper wiring lines is formed on the sealing layer in a region outside the semiconductor construct,
- wherein the insulating film has one or more layers and comprises at least a passivation film;
- wherein the prepreg is a sheetlike semi-cured resin;
- and
- wherein stacking the sealing layer comprises laying a prepreg on the semiconductor constructs and the base plate and heating and pressurizing the prepreg toward the base plate to form the sealing layer, such that the semiconductor constructs are embedded in the sealing layer and each of the columnar electrodes penetrates through the sealing layer, whereby the top surfaces of the columnar electrodes are exposed from the upper surface of the sealing layer.
6 more elements
Dependencies are inferred from the claim text.