Dicing Structures for Semiconductor Substrates and Methods of Fabrication Thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsien-Wei Chen
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Abstract
Dicing structures for semiconductor substrates and methods of fabrication thereof are described. In one embodiment, a semiconductor wafer includes a first chip disposed in a substrate, a second chip disposed adjacent the first chip and disposed in the substrate, and a dicing street disposed between the first and the second chip. A first and a second metal level are disposed over the dicing street, wherein the second metal level is disposed above the first metal level. A first alignment mark is disposed in the first metal level above a first portion of the dicing street, and first metal features disposed in the second metal level above the first portion of the dicing street.
Claims20
A method of fabricating a semiconductor device, the method comprising:
- forming dicing streets and cell regions comprising active devices in a substrate, the dicing streets separating the cell regions;
- forming a first alignment mark disposed in a first metal level above a first portion of the dicing street;
- and
- forming first metal features in a second metal level above the first portion of the dicing street, the second metal level disposed above the first metal level.
A method of manufacturing a dicing structure in a semiconductor wafer, the method comprising:
- designing an alignment mark in a metal level;
- placing metal features on all upper metal levels above the alignment mark;
- placing metal features on all lower metal levels below the alignment mark;
- measuring the noise generated by the metal features from all the upper and lower metal levels during an aligning process;
- removing metal features from a highest level of the lower metal levels if the measured noise is unacceptable;
- and
- repeating the above steps of measuring and removing until the measured noise is acceptable.
A method of fabricating a semiconductor device, the method comprising:
- fabricating on a substrate a plurality of die regions separated by scribe regions;
- depositing a dielectric layer over the die regions and over the scribe regions;
- embedding an alignment mark in the dielectric layer and simultaneously embedding interconnect structures in the dielectric layer over the die regions, the alignment mark having a substantially flat uppermost surface extending contiguously between lateral boundaries of the alignment mark, the uppermost surface of the alignment mark being substantially level with the uppermost surface of the dielectric layer;
- depositing a second dielectric layer over the alignment mark and the interconnects;
- embedding second interconnects in the second dielectric layer, the second interconnects being laterally separated by first distances and a portion of each of at least two of the second interconnects aligned over and within the lateral boundaries of the alignment mark, the plurality of the second interconnects disposed in a plurality of rows;
- and
- depositing a contiguous third dielectric over the second interconnects, third dielectric material having a bottommost surface in direct physical contact with an uppermost surface of the second dielectric layer;
- and
- embedding third interconnects in the third dielectric layer forming a third metal level in a, wherein a portion of each of a plurality of third interconnects is aligned directly over and within lateral boundaries of the alignment mark.
Dependencies are inferred from the claim text.