Electromagnetic bandgap structure for three dimensional ics

An electromagnetic bandgap (EBG) structure in a three-dimensional (3D) integrated circuit (IC) package, comprising:

• a plurality of EBG cells;
• wherein each of the EBG cells includes one or more of:
• a plurality of first conductive line layers, wherein wire segments on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at bottom of the EBG cell;
• a pair of through-substrate-vias (TSVs) above the plurality of bottom conductive line layers, wherein the pair of TSVs penetrate a first IC die and are connected to a high voltage source and a low voltage source, respectively;
• a pair of micro bumps above a dielectric layer above the pair of TSVs in an oxide layer, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die;
• said plurality of second conductive line layers being above the pair of micro bumps, wherein wire segments on at least one of the second conductive line layers are each connected to a respective one of a high voltage source and a low voltage source and are oriented to form a second mesh structure of the EBG cell;
• a plurality of bridges, wherein at least one of the bridges includes one or more connecting wires for connecting the high and low voltage source connecting wire segments in a first of the EBG cells to wire segments in a second of the EBG cells.

A method for forming an electromagnetic bandgap (EBG) structure in a three-dimensional (3D) integrated circuit (IC) package, comprising:

• forming a plurality of EBG cells;
• wherein each of the EBG cells includes one or more of:
• a plurality of first conductive line layers beneath a first integrated circuit (IC) die, wherein wire segments on at least one of the first conductive line layers are each connected to one of a high voltage source and a low voltage source and are oriented to form a first mesh structure at a bottom of the EBG cell;
• a pair of through-substrate-vias (TSVs) above the plurality of bottom conductive line layers, wherein the pair of TSVs penetrate the first IC die and are connected to a high voltage source and a low voltage source, respectively;
• a pair of micro bumps above a dielectric layer above the pair of TSVs in an oxide layer, wherein the micro bumps connect the TSVs of the first IC die with a plurality of second conductive line layers formed on a second IC die;
• said plurality of second conductive line layers being above the pair of micro bumps, wherein wire segments on at least one of the second conductive line layers are each connected to a respective one of a high voltage source and a low voltage source and are oriented to form a second mesh structure of the EBG cell;
• and
• forming a plurality of bridges, wherein at least one of the bridges includes one or more connecting wires for connecting the high and low voltage source connecting wire segments in a first of the EBG cells to wire segments in a second of the EBG cells.